试看120分钟做受小视频,打开在线看黄色网站导航,日韩欧美福利,久久xx,亚州大毛片视频,日韩在线一区二区三区免费视频,久久er热这里只有精品免费

崗位職責(zé):
1.RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2.Design flow/methodology development and innovation for front-end design challenges.
3.Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任職要求:
1.MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2.New graduate or 3 years working experience.
3.Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4.Familiar with tcl/Perl/Python program.